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Video Processing with Nexys A7 100T: FPGA Trainer Board The system comprises the following Xilinx IP on the single ZCU102: Xilinx This Demo is the Real Time Canny Edge Detection of 1080p
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Enabling AMD 2D Hardware Acceleration for Video API and Applications - Solomon Chiu
HDMI Video Pipeline Design Implementation on Zynq 7000 SoC (Pynq-Z1)
Real Time Canny Edge Detection of 1080p Video with Zybo FPGA
StreamForge Demo Video
Integrating Hardware-accelerated Video Decoding with the Display Stack - Paul Kocialkowski, Bootlin
M15 - 1 - Video Subsystem Overview
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Last Updated: June 21, 2026
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