Smartdebug Liveprobe

Smartdebug Liveprobe Information Guide

1. Overview to Smartdebug Liveprobe
2. Core Information
3. History
4. Deep Dive
5. Summary

Overview to Smartdebug Liveprobe

Probe Insertion routes any internal signals in the FPGA design to available unused I/O pins without disturbing the existing placed ... Fabric memory debug allows asynchronous read and write to the block rams like LSRAM and the micro SRAM. The secure NVM debug used to debug the user data and the user initialization client data configured in Libero design. The uPROM debug is used to debug the client data configured in Libero design. Learn how to read the Fabric Digest and sNVM Digest of a Microchip FPGA using This video will demonstrate some of the debug features of

Microchip's Libero SoC allows the usage of 3rd party simulators. Because of that, Active-HDL's fast and comprehensive tools are ...

Core Information

History

SmartDebug demonstration

Fabric Memory Debug using SmartDebug

How to Debug DDR Memory Interfaces Using SmartDebug

sNVM Debug using SmartDebug

uPROM Memory Debug using SmartDebug

How to Read Fabric and sNVM Digest in SmartDebug | Libero SoC 2025.1

Debugging PolarFire® SoC - Smart Debug

Microsemi Webinar: Active Probe (June 2018)

3.5 - Active-HDL™ 3rd Party Flows: Simulation & Debugging with Microchip Libero SoC

Deep Dive

Data is compiled from public records and verified media reports.

Last Updated: June 18, 2026

Summary

Disclaimer: Disclaimer: Details estimates are based on publicly available data, media reports, and financial analysis. Actual numbers may vary.